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dear customers, about the change in the name such as "oki electric industry co. ltd." and "oki" in documents to oki semiconductor co., ltd. the semiconductor business of oki electric industry co., ltd. was succeeded to oki semiconductor co., ltd. on oc tober 1, 2008. therefore, please accept that although the terms and marks of "oki electric indust ry co., ltd.", ?oki electric?, and "oki" remain in the documents, they all have been changed to "oki semiconductor co., ltd.". it is a change of the company name, the co mpany trademark, and the logo, etc. , and not a content change in documents. october 1, 2008 oki semiconductor co., ltd. 550-1 higashiasakawa-cho, hachio ji-shi, tokyo 193-8550, japan http://www.okisemi.com/en/
1/18 ? semiconductor msm5116405c description the msm5116405c is a 4,194,304-word 4-bit dynamic ram fabricated in oki's silicon-gate cmos technology. the msm5116405c achieves high integration, high-speed operation, and low-power consumption because oki manufactures the device in a quadruple-layer polysilicon/double-layer metal cmos process. the msm5116405c is available in a 26/24-pin plastic soj or 26/24-pin plastic tsop. features ? 4,194,304-word 4-bit configuration ? single 5 v power supply, 10% tolerance ? input : ttl compatible, low input capacitance ? output : ttl compatible, 3-state ? refresh : 4096 cycles/64 ms ? fast page mode with edo, read modify write capability ? cas before ras refresh, hidden refresh, ras -only refresh capability ? multi-bit test mode capability ? package options: 26/24-pin 300 mil plastic soj (soj26/24-p-300-1.27) (product : msm5116405c-xxsj) 26/24-pin 300 mil plastic tsop (tsopii26/24-p-300-1.27-k) (product : msm5116405c-xxts-k) (tsopii26/24-p-300-1.27-l) (product : msm5116405c-xxts-l) xx indicates speed rank. product family ? semiconductor msm5116405c 4,194,304-word 4-bit dynamic ram : fast page mode type with edo msm5116405c-70 70 ns 130 ns 90 ns 440 mw 550 mw family access time (max.) cycle time (min.) standby (max.) power dissipation msm5116405c-50 t rac 50 ns 35 ns t aa 25 ns 20 ns t cac 13 ns 20 ns t oea 13 ns msm5116405c-60 60 ns 110 ns 495 mw 30 ns 15 ns 15 ns operating (max.) 5.5 mw e2g0107-18-42 preliminary this version: apr. 1998
2/18 ? semiconductor msm5116405c pin configuration (top view) 26/24-pin plastic soj 26/24-pin plastic tsop (k type) 26/24-pin plastic tsop (l type) pin name function a0 - a9, address input ras row address strobe cas column address strobe dq1 - dq4 data input/data output oe output enable we write enable v cc power supply (5 v) v ss ground (0 v) a10r, a11r 3 4 5 9 10 11 12 13 dq2 a0 a1 a2 a3 v cc 24 23 22 18 17 16 15 14 dq3 a7 a6 a5 a4 v ss 2 dq1 25 dq4 1 v cc 26 v ss 3 4 5 9 10 11 12 13 24 23 22 18 17 16 15 14 2 25 1 26 24 23 22 18 17 16 15 14 3 4 5 9 10 11 12 13 25 2 26 1 6 a11r 21 a9 21 21 6 8 a10r 19 a8 19 19 8 6 8 dq2 a0 a1 a2 a3 v cc dq1 v cc a11r a10r dq3 a7 a6 a5 a4 v ss dq4 v ss a9 a8 dq3 a7 a6 a5 a4 v ss dq4 v ss a9 a8 dq2 a0 a1 a2 a3 v cc dq1 v cc a11r a10r we cas we cas cas we ras oe ras oe oe ras note : the same power supply voltage must be provided to every v cc pin, and the same gnd voltage level must be provided to every v ss pin.
3/18 ? semiconductor msm5116405c block diagram timing generator ras cas timing generator internal address counter row address buffers v cc v ss on chip iv cc generator row de- coders word drivers memory cells refresh control clock sense amplifiers column decoders write clock generator i/o selector output buffers we oe 4 dq1 - dq4 4 4 4 4 4 input buffers 4 10 a0 - a9 12 10 10 2 a10r, a11r column address buffers on chip v bb generator
4/18 ? semiconductor msm5116405c electrical characteristics absolute maximum ratings voltage on any pin relative to v ss short circuit output current power dissipation operating temperature storage temperature v in , v out symbol i os p d * t opr t stg C0.5 to v cc + 0.5 50 1 0 to 70 C55 to 150 rating ma w c c parameter v unit voltage on v cc supply relative to v ss v cc C0.5 to 7 v recommended operating conditions *: ta = 25 c power supply voltage input high voltage input low voltage v cc symbol v ss v ih v il 5.0 0 typ. parameter 4.5 0 2.4 C0.5 *2 min. 5.5 0 v cc + 0.5 *1 0.8 max. (ta = 0c to 70c) v unit v v v notes : *1. the input voltage is v cc + 2.0 v when the pulse width is less than 20 ns (the pulse width is with respect to the point at which v cc is applied). *2. the input voltage is v ss C 2.0 v when the pulse width is less than 20 ns (the pulse width is with respect to the point at which v ss is applied). capacitance input capacitance (a0 - a9, a10r, a11r) input capacitance ( ras , cas , we , oe ) output capacitance (dq1 - dq4) c in1 symbol c in2 c i/o 5 7 7 max. pf unit pf pf parameter (v cc = 5 v 10%, ta = 25c, f = 1 mhz) typ.
5/18 ? semiconductor msm5116405c dc characteristics notes : 1. i cc max. is specified as i cc for output open condition. 2. the address can be changed once or less while ras = v il . 3. the address can be changed once or less while cas = v ih . i oh = C5.0 ma output high voltage i ol = 4.2 ma output low voltage 0 v v i 6.5 v; all other pins not input leakage current under test = 0 v dq disable output leakage current 0 v v o v cc ras , cas cycling, average power t rc = min. supply current (operating) ras , cas = v ih power supply ras , cas current (standby) ras cycling, average power cas = v ih , supply current t rc = min. ( ras -only refresh) ras = v ih , power supply cas = v il , current (standby) dq = enable average power cas before ras supply current ( cas before ras refresh) ras = v il , average power cas cycling, supply current t hpc = min. (fast page mode) v oh v ol i li i lo i cc1 i cc2 i cc3 i cc5 i cc6 i cc7 3 v cc C0.2 v ras cycling, parameter condition msm5116405 c-50 msm5116405 c-60 msm5116405 c-70 (v cc = 5 v 10%, ta = 0c to 70c) symbol min. 2.4 0 C10 C10 max. v cc 0.4 10 10 100 2 1 100 100 90 5 min. 2.4 0 C10 C10 max. v cc 0.4 10 10 90 2 1 90 90 80 5 min. 2.4 0 C10 C10 max. v cc 0.4 10 10 80 2 1 80 80 70 5 unit v v m a m a ma ma ma ma ma ma note 1, 2 1, 2 1, 2 1, 3 1 1
6/18 ? semiconductor msm5116405c ac characteristics (1/2) random read or write cycle time read modify write cycle time fast page mode cycle time fast page mode read modify write cycle time access time from ras access time from cas access time from column address access time from cas precharge cas to data output buffer turn-off delay time transition time ras precharge time ras pulse width ras pulse width (fast page mode with edo) ras hold time cas pulse width cas hold time ras to cas delay time ras to column address delay time cas to ras precharge time row address set-up time row address hold time column address set-up time column address hold time column address to ras lead time access time from oe oe to data output buffer turn-off delay time refresh period ras hold time referenced to oe ras hold time from cas precharge t rc t rwc t hpc t hprwc t rac t cac t aa t cpa t cez t t t rp t ras t rasp t rsh t cas t csh t rcd t rad t crp t asr t rah t asc t cah t ral t oea t oez t ref t roh t rhcp output low impedance time from cas t clz cas precharge time (fast page mode with edo) t cp parameter msm5116405 c-60 msm5116405 c-70 msm5116405 c-50 (v cc = 5 v 10%, ta = 0c to 70c) note 1, 2, 3, 12, 13 symbol note 4, 5, 6 4, 5 4, 6 4 7, 8 5 6 4 7 4 3 max. 60 15 30 35 15 50 10,000 100,000 10,000 45 30 15 15 64 unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns min. 84 110 20 58 0 0 1 30 50 50 7 7 7 35 11 9 5 0 7 0 7 25 0 7 30 max. 50 13 25 30 13 50 10,000 100,000 10,000 37 25 13 13 64 min. 124 160 30 78 0 0 1 50 70 70 13 10 13 45 14 12 5 0 13 0 13 35 0 13 40 max. 70 20 35 40 20 50 10,000 100,000 10,000 50 35 20 20 64 min. 104 135 25 68 0 0 1 40 60 60 10 10 10 40 14 12 5 0 10 0 10 30 0 10 35 data output hold after cas low we to data output buffer turn-off delay time ras to data output buffer turn-off delay time t doh t wez t rez 7, 8 7 15 15 ns ns ns 5 0 0 13 13 5 0 0 20 20 5 0 0 oe hold time from cas (dq disable) t cho ns 5 5 5
7/18 ? semiconductor msm5116405c ac characteristics (2/2) write command pulse width write command to cas lead time write command to ras lead time data-in set-up time cas to we delay time ras to we delay time column address to we delay time ras to cas hold time ( cas before ras ) cas active delay time from ras precharge data-in hold time write command hold time oe command hold time oe to data-in delay time write command set-up time ras to cas set-up time ( cas before ras ) we to ras precharge time ( cas before ras ) we hold time from ras ( cas before ras ) ras to we set-up time (test mode) cas precharge we delay time ras to we hold time (test mode) t wp t cwl t rwl t ds t cwd t rwd t awd t csr t chr t rpc t dh t wch t oeh t oed t wcs t wrp t wrh t wts t cpwd t wth msm5116405 c-60 msm5116405 c-70 msm5116405 c-50 (v cc = 5 v 10%, ta = 0c to 70c) note 1, 2, 3, 12, 13 parameter symbol max. 10 10 10 ns ns ns 10 10 10 10 10 10 note 11 10 10 10 11 10 10 10 ns 10 10 min. 10 10 10 0 34 79 49 5 10 5 10 10 10 15 0 54 max. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns unit ns min. 7 7 7 0 30 67 42 5 10 5 7 7 7 13 0 47 max. min. 10 13 13 0 44 94 59 5 10 5 13 13 13 20 0 64 read command set-up time read command hold time read command hold time referenced to ras t rcs t rch t rrh 9 9 ns ns ns 0 0 0 0 0 0 0 0 0 we pulse width (dq disable) t wpe 10 ns 710 oe precharge time t oep 10 ns 710 oe command hold time t och 10 ns 710
8/18 ? semiconductor msm5116405c notes: 1. a start-up delay of 200 m s is required after power-up, followed by a minimum of eight initialization cycles ( ras -only refresh or cas before ras refresh) before proper device operation is achieved. 2. the ac characteristics assume t t = 2 ns. 3. v ih (min.) and v il (max.) are reference levels for measuring input timing signals. transition times (t t ) are measured between v ih and v il . 4. this parameter is measured with a load circuit equivalent to 2 ttl loads and 100 pf. 5. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only. if t rcd is greater than the specified t rcd (max.) limit, then the access time is controlled by t cac . 6. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, then the access time is controlled by t aa . 7. t cez (max.), t rez (max.), t wez (max.) and t oez (max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. t cez and t rez must be satisfied for open circuit condition. 9. t rch or t rrh must be satisfied for a read cycle. 10. t wcs , t cwd , t rwd , t awd and t cpwd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. if t cwd 3 t cwd (min.) , t rwd 3 t rwd (min.), t awd 3 t awd (min.) and t cpwd 3 t cpwd (min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 11. these parameters are referenced to the cas leading edge in an early write cycle, and to the we leading edge in an oe control write cycle, or a read modify write cycle. 12. the test mode is initiated by performing a we and cas before ras refresh cycle. this mode is latched and remains in effect until the exit cycle is generated. in a test mode ca0 and ca1 are not used and each dq pin now accesses 4-bit locations. since all 4 dq pins are used, a total of 16 data bits can be written in parallel into the memory array. in a read cycle, if 4 data bits are equal, the dq pin will indicate a high level. if the 4 data bits are not equal, the dq pin will indicate a low level. the test mode is cleared and the memory device returned to its normal operating state by performing a ras -only refresh cycle or a cas before ras refresh cycle. 13. in a test mode read cycle, the value of access time parameters is delayed for 5 ns for the specified value. these parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet.
9/18 ? semiconductor msm5116405c write cycle (early write) "h" or "l" ras cas v ih v il C C v ih v il C C dq v oh v ol C C address v ih v il C C we v ih v il C C oe v ih v il C C t rc t ras t rp t crp t csh t crp t rcd t rsh t cas t rad t asr t rah t asc t cah t ral row column t rcs t rrh t rch t aa t roh t oea t cac t rac t oez t cez open t clz valid data-out t rez "h" or "l" ras cas v ih v il C C v ih v il C C dq v ih v il C C address v ih v il C C we v ih v il C C oe v ih v il C C t rc t ras t rp t crp t rcd t csh t rsh t crp t cas t rad t rah t asr t asc t cah row column t wcs t wch t ds t dh valid data-in t wp t ral open t rwl t cwl e2g0100-17-41m timing waveform read cycle
10/18 ? semiconductor msm5116405c read modify write cycle "h" or "l" ras cas v ih v il C C v ih v il C C dq v i/oh v i/ol C C address v ih v il C C we v ih v il C C oe v ih v il C C t rwc t ras t rp t crp t csh t rcd t crp t rsh t cas t asr t rah t asc t cah row column t cwd t cwl t rwd t rwl t wp t aa t awd t oea t oed t cac t rac t oez t ds t dh t clz valid data-out valid data-in t rad t rcs t oeh
11/18 ? semiconductor msm5116405c fast page mode read cycle (part-1) fast page mode read cycle (part-2) C C C C C C C C v ih ras address we dq cas oe C C C C v il v ih v il v ih v il v ih v il v ih v il v oh v ol row column t crp t crp t rp t rasp t cas t csh "h" or "l" column column t rcd t cp t cas t cas t hpc t cp t cah t asc t rad t rcs t rch t rac t aa t cac t clz t wez t oea valid data-out valid data-out valid data-out t rah t asr t cah t asc t cah t asc t cac t aa t doh t cez t cpa t aa t cac t rcs t wpe t rhcp e e e e e e e e v ih ras address we dq cas oe C C C C v il v ih v il v ih v il v ih v il v ih v il v oh v ol row column t crp t rp t rasp t cas t csh "h" or "l" column column t rcd t cp t cas t cas t hpc t cah t asc t rad t rcs t aa t rrh t cac t clz t cpa t oea valid data-out valid* data-out t rah t asr t cah t asc t cah t asc t rac valid data-out t aa t cac t doh valid* data-out t cac t rez t oez t oez t cho t och t aa t oea t oep t oep t oea * : same data, t cp t rhcp
12/18 ? semiconductor msm5116405c fast page mode write cycle (early write) fast page mode read modify write cycle C C C C C C C C v ih ras address we dq cas oe C C C C v il v ih v il v ih v il v ih v il v ih v il v ih v il t asr row column t crp t rp t rasp t cas t csh t rah column column t rcd t cp t cas t cas t hpc t cp t hpc t asc t cah t cah t cah t asc t asc t rad "h" or "l" t dh t ds t wch valid data-in t ds t dh t ds t dh t wch t wch t rsh valid data-in valid data-in t wcs t wcs t wcs e e e e e e e e v ih ras address we dq cas oe C C C C v il v ih v il v ih v il v ih v il v ih v il v i/oh v i/ol t asr row column t rasp t cwd t rah column t rcd t cp t asc t cah t cpa t asc t rad t rwd "h" or "l" valid data-out t oez t oed t ds t wp t awd t rcs t cwd t rwl t cac t awd t rac t wp t clz t dh t oeh valid data-in t oea valid data-out t oez t oed t cac t dh t oeh valid data-in t oea t clz t ds t aa t aa t rcs t cah t cpwd t hprwc t crp t cwl
13/18 ? semiconductor msm5116405c ras -only refresh cycle cas before ras refresh cycle f p q r s \ ] ^ k l m v ih v il ras t rp C C cas v ih v il C C v ih v il we v v "h" or "l" t rc t ras t rpc t chr t rp t rpc t cp t csr t wrp t wrh t cez t wrp open C C ol oh C C dq note: oe , address = "h" or "l" : f m n o p q r s k ] ^ _ v ih v il ras t t rp t C C cas v ih v il v ih v il C C address ras "h" or "l" rc note: we , oe = "h" or "l" t crp t rpc t asr t rah row v oh v ol C C dq t cez C C open
14/18 ? semiconductor msm5116405c hidden refresh read cycle hidden refresh write cycle C C C C C C C C v ih ras address we dq cas oe C C C C v il v ih v il v ih v il v ih v il v ih v il v ih v il "h" or "l" t asr row column t crp t rc t asc t rp t ras t rcd t rsh t rad t cah t rah t ral t rwl t chr t ras t rc t rp t ds t wp t wch t dh valid data-in t wcs ras cas address oe v ih v il C C v ih v il C C v ih v il C C v ih v il C C "h" or "l" we v ih v il C C dq v oh v ol C C t rc t rc t ras t rp t ras t rp t crp t rcd t rsh t chr t rad t asr t rah t asc t cah row column t rcs t ral t rrh t aa t roh t oea t cac t rac t clz t oez valid data-out open t cez t rez
15/18 ? semiconductor msm5116405c test mode initiate cycle v ih v il ras cas v ih v il C C C C t ras "h" or "l" v oh v ol C C v ih v il C C open t rc t wth t rpc t wts t cp t csr t chr t off note: oe , address = "h" or "l" t rp we dq
16/18 ? semiconductor msm5116405c (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). soj26/24-p-300-1.27 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.80 typ. mirror finish
17/18 ? semiconductor msm5116405c (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.29 typ. tsop ii 26/24-p-300-1.27-k mirror finish
18/18 ? semiconductor msm5116405c (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). package material lead frame material pin treatment solder plate thickness epoxy resin 42 alloy solder plating 5 m m or more package weight (g) 0.29 typ. tsop ii 26/24-p-300-1.27-l mirror finish

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